The present invention relates to semiconductor processing. More particularly, it relates to a semiconductor process to planarize a semiconductor surface. Even more particularly, it relates to a semiconductor process to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) planarization process.
The process of planarizing a semiconductor surface is important for advanced VLSI (Very Large Scale Integration) technology. A planar semiconductor surface provides a surface free from large variations in topography which reduces process problems associated with forming subsequent devices or layers on the semiconductor surface. Conventional semiconductor surface planarization processes mainly rely on Chemical Mechanical Polishing (CMP). CMP processes introduce defects such as particulate contamination, scratches, and chatter markers. Also, conventional CMP processes introduce xe2x80x9cdishingxe2x80x9d effects across diverse dimensions resulting in film nonuniformities along the surface of the semiconductor.
The current invention will describe a method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process. Shallow recesses are formed in a semiconductor substrate. A filling material is then deposited on the semiconductor substrate to fill the shallow recesses. The thickness of the filling material is approximately equal to the depth of the shallow recesses. A selectively etchable material is then formed on the filling material. The selectively etchable material is patterned to form segments equal to the pattern of the shallow recesses and aligned with the shallow recesses. The segments of selectively etchable material serve as a mask to define exposed portions of the filling material to be removed. After removal of the exposed portions of the filling material, the segments of selectively etchable material are also removed. The remaining filling material in the shallow recesses forms fences which extend above the semiconductor surface. The fences are removed and results in a planar semiconductor surface.
The advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.